Nov 13 – 15, 2024
Hotel Lahan, Pohang, Korea
Asia/Seoul timezone

Design of the Korea-4GSR Machine Interlock System

Nov 14, 2024, 1:00 PM
1h 30m
2F Poster Hall

2F Poster Hall

Board: WG1-39
Poster ICABU WG1. Accelerator Systems ICABU Poster Session

Speaker

Yunho Kim (Pohang Accelerator Laboratory)

Description

MIS (Machine Interlock System) for Korea-4GSR is a system that prevents operations that may cause harm to related devices when a malfunction or a harmful situation occurs in each device configured throughout the accelerator during accelerator operation. It is an essential element of accelerator operation. MIS is classified by area, level, and device according to each accelerator operation policy and aims to protect each device. In the MPS (Machine Protection System), MIS mainly covers signals with relatively slow response speeds and low importance among various classifications of signals. For signals generated by an interlock situation, which are recognized by the central device from local devices and transmitted to the final destination, differences in speed exist depending on the route. However, MIS is designed with minimized signal routes so that the difference in speed by signal will be minimal. The controller of MIS is a PLC (Programmable Logic Controller), which is widely used in various fields of industry and experimental physics. Since various PLC guidelines are provided for securing system reliability and responding to failures, configuring a more robust system is more accessible with PLC than with other types of controllers. MIS is basically configured to ensure high availability by considering device failure situations (PLC product failure, power outage, etc.). In addition, a high-reliability design is essential, considering the safety and reliability of the data. The connection between the Central and Local PLC uses industrial Ethernet protocols such as Profinet to intimately exchange data. It also features the ability to provide services for users by linking with EPICS IOC.

Contribution track ICABU WG1. Accelerator Systems
Paper submission Plan No
Best Presentation No

Primary author

Yunho Kim (Pohang Accelerator Laboratory)

Co-authors

Jinsung Yu (Pohang Accelerator Laboratory) Dr Seung-Hee Nam (Pohang Accelerator Laboratory) ryu yeunchan (Pohang Acclerator Labatory) sohee park (pohang accelator laboratory)

Presentation materials

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